.png)
Committed to impart better learning through value based education and practical acquisition of knowledge amongst the students.
A unique institution that provides an array of engineering and management courses to choose from.
Creating a world of exploration, critical thinking and discovery for better knowledge and understanding .
With the focus on industry specific knowledge, our students are placed in the top-notch organisations.
At MIET, education is about more than earning a degree. Here, you'll be a part of enduring university traditions and have new experiences that you'll remember for a lifetime.
An environment which is specially created to provide all the state-of-art facilities for optimum comfort like home.
Be a part of MIET because 'Whats starts here changes the world'. Make your mark with us.
Creating a world of exploration, critical thinking and discovery for better knowledge and understanding .
The institute provides a summer training of UTLP Embedded Program that was proposed by WIPRO. The major area we cover in this training will be related to Xilinx & VHDL / Verilog Languages and FPGA. After this training the students will be able to work on advanced tools based on VHDL/Verilog and FPGA.
The college will provide 04 weeks summer training certificate, to all those students who will participate in both e-yantra & UTLP training programme under Integrated Training Program.
| Prerequisite | Hands on experience on "C" for embedded based applications |
| Eligible Branches | EC/ EE/ CS/ IT Students |
| Eligible Students (Year) | 2nd & 3rd Year Students |
| Program time | Just after End Semester Examinations (Winter & Summers) |
| Duration | Two Week |
| Open to outside students | Yes |
| Courseware | Yes |
| Evaluation if Any | No |
| Trainers | Internal |
| Certificate | Internal |
| Course Coordinators |
Mr. Ankur Garg, Faculty CS Department, in Azim Premji -Block (M-201). Contact No: 9358808947 Mr. H. P. Singh, Faculty EC Department, in Azim Premji -Block (M-513). Contact No: 7895528188 |
| DAY | Lecture Timing | Course Content | Instructor |
| Day 1 | 10.00 am to 4.00 pm | Introduction to Xilinx & VHDL / Verilog Languages | Mr. H. P. Singh |
| Day 2 | 10.00 am to 4.00 pm | Verilog Language | Mr. H. P. Singh |
| Day 3 | 10.00 am to 4.00 pm | VHDL Language | Mr. Varun Singhal |
| Day 4 | 10.00 am to 4.00 pm | VHDL Language | Mr. Varun Singhal |
| Day 5 | 10.00 am to 4.00 pm |
Introduction to Embedded Systems UTLP Tutorials ULK Control Panel Eclipse |
Mr. Ankur Garg Mr. Amit Garg |
| Day 6 | 10.00 am to 4.00 pm | Tutorials on FPGA using UTLP | Mr. H. P. Singh |
| Day 7 | 10.00 am to 4.00 pm |
UTLP Interfaces based on FPGA: LED 7Seg LED Keypad CLCD |
Mr. H. P. Singh |
| Day 8 | 10.00 am to 4.00 pm | Hands on session – on FPGA | Mr. H. P. Singh |
| Day 9 | 10.00 am to 4.00 pm |
External Interfaces on UTLP & there Applications GLCD TOUCH Panel |
Mr Varun Singhal Mr Neeraj Joshi |
| Day 10 | 10.00 am to 4.00 pm | Major Project Allocation |
Mr. Varun Kr. Singhal Mr. Neeraj Joshi Mr. H. P. Singh |
| Day 11 | 10.00 am to 4.00 pm | Project Work |
Mr. Varun Kr. Singhal Mr. Neeraj Joshi Mr. H. P. Singh |
| Day 12 | 10.00 am to 4.00 pm | Project Presentation & Valedictory Function |
Mr. Varun Kr. Singhal Mr. Neeraj Joshi Mr. H. P. Singh |
The students will be able to gain the knowledge of
• Embedded Programming Concepts
• Project Development through UTLP Embedded Programming
(Mr Amit Garg) MCA Department
(Mr. Ankur garg) CSE Department
(Mr. H. P. Singh) EC Department
